1. Field of the Invention
This invention relates generally to semiconductor integrated circuits and more particularly to high density packaging for integrated circuits.
2. Description of the Prior Art
There is a continuing trend in the electronic industry to pack more and more electronic devices into smaller and smaller spaces. The reasons for this trend are many. One obvious reason is that electronic assemblies can be made smaller and more convenient. Another, more subtle reason for miniaturization is to minimize inter-device lead length which is often a critical factor in the high frequency response of an electronic circuit, particularly in the case of high speed digital devices.
There are two well accepted methods for increasing the density of electronic circuits. One method is to create ever more semiconductor interconnections at the chip (also known as the "die") level. Great strides have been accomplished with this method in the last few years with the L.S.I. and V.L.S.I. technologies. The second method for increasing the density of electronic circuits involves maximizing the use of printed circuit (P.C.) real estate by packaging semiconductor chips more efficiently. It is to the second method of increasing the density of electronic circuits that this invention is directed.
Large plastic and ceramic DIPs (Dual In-Line Packages) having from 14 to 64 lead pins are well known to those persons familiar with electronics. Unfortunately, the larger DIP sizes, which can be over three inches in length, exhibit high pin-to-pin capacitance which can seriously limit the high speed response of the chips. For instance, a 64 pin DIP can have up to a 7 pF pin-to-pin capacitance and a 1.1 ohm lead resistance at the relatively low switching speed of 1 MHz.
A partial solution to this problem is found with the QUIP (Quad In-Line Package) which includes two rows of lead-pins instead of one along each longitudinal edge, so that a QUIP can contain its 64 pins in a little over 11/2 inches as opposed to the DIP's over 3 inch length. In consequence, a QUIP exhibits a maximum 3 pF pin-to-pin capacitance and a maximum 0.3 ohm lead resistance at 1 MHz, which is a substantial improvement over the DIP.
An even more attractive solution to the high density packaging problem is found with the chip carrier concept. A chip carrier consists of a small, square ceramic support barely larger than the integrated circuit die it holds and has screen printed metalized traces extending from internal bonding pads of the die to the external terminal contacts of the chip carrier. Square chip carriers occupy only one-third to one-sixth the area of a DIP, and a 64 lead chip carrier will have a 2 pF maximum inter-lead capacitance and a 0.1 ohm maximum lead resistance, resulting in an upper frequency operational limit about twice that of a DIP.
DIPs, QUIPs and chip carriers suffer from at least two common problems. First of all, all three of the aforementioned packages position the integrated circuit die parallel to the P.C. board, which is a very inefficient use of P.C. board space. Secondly, the integrated circuit chips within each of the packages can only be coupled to other chips by routing signals through a first lead-pin, a P.C. board trace and a second lead-pin of another integrated circuit package. These extremely long signal paths through a P.C. board trace severely limits the upper frequency response of the final electronic circuit.
Partially addressing the problem of long signal paths is the DIP motherboard concept. In this concept, a motherboard having DIP compatible lead-pins supports a number of directly soldered leadless chip carriers. While a DIP motherboard eliminates the need for many signal paths through a P.C. board's traces, it is a relatively inflexible device allowing only a fixed set of interconnections between the individual chip carriers.
A number of motherboard type packages have been made the object of U.S. patents. For example, R. Dennis et al, in U.S. Pat. No. 3,982,159 discloses a leadless package retaining frame including a framework having spring bias means for holding integrated circuit chips in contact with conductor pads on a motherboard. Also, N. Peterson, in U.S. Pat. No. 3,899,720 teaches a package for microwave integrated circuits having a plurality of flat integrated circuits assembled on a common circuit completing board.
A problem with even the motherboard concept is that a signal still needs to be brought out of one chip carrier down to the motherboard and then back up to another chip carrier. Thus, a problem that the prior art apparently does not address is how to couple signals from one chip carrier directly to another chip carrier without any intermediary signal path whatsoever.